This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-342357, Dec. 1, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor integrated circuit provided with a circuit for limiting to a predetermined value or less a change in a potential which has been boosted from a power supply potential, and more particularly to a nonvolatile semiconductor memory integrated circuit or the like having a row decoder circuit for outputting the boosted potential to word lines.
In the nonvolatile semiconductor memory integrated circuit, it is necessary to apply the potential boosted to a level higher than the normal potential of the power supply at the time of writing or erasing data.
FIG. 5 is a circuit diagram showing an extracted part of a row decoder circuit and a prior art potential control circuit for outputting a potential boosted to a level higher than the normal power supply at the time of writing data in a conventional nonvolatile semiconductor memory integrated circuit.
In FIG. 5, a transistor 51 is provided at a final stage of the row decoder circuit, and the transistor 51 outputs the boosted potential to word line WL at the time of data writing. To node A to which one of the source or the drain of this transistor 51 is connected, a potential which is boosted at the time of driving the word line WL is supplied. A node B to which the other of the source and the drain of the transistor 51 is connected is connected to the corresponding word line WL. Furthermore, between a node C to which the boosted potential is supplied and a node D to which the gate of the transistor 51 is connected, the source-drain path of the transistor 52 is inserted. To a node E of the gate of the transistor 52, a predetermined bias potential is supplied.
Furthermore, between the node D and a node F to which the boosted potential is supplied, a potential limiting circuit 53 for limiting the potential at the node D to less than the predetermined value is inserted. This potential limiting circuit 53 comprises two transistors 54 and 55 in which a gate is connected to respective source and the source-drain paths are connected in series. In this case, the transistors 54 and 55 are of N-channel enhancement type.
Next, an operation of the circuit of FIG. 5 will be explained by referring to the timing chart of FIGS. 6A through 6D. Suppose that the boosted potential V1 is supplied to the node E of the gate of the transistor 52 at the time of data writing.
In the beginning, a boosted potential V1 is supplied to the node C at the time of data writing to the memory cell not shown connected to the word line WL. As shown in FIG. 6A, when the node C is set to the boosted potential V1, the transistor 52 is turned on. Then, as shown in FIG. 6B, the node D is charged to V1xe2x88x92Vt through this transistor 52 (where Vt denotes a threshold voltage of the transistor 52), and the transistor 52 is cut off.
Next, as shown in FIG. 6C, the potential of the node A is changed from the ground potential to the boosted potential V1. Since the transistor 52 has been cut off and the node D is in the floating state, the rise in the channel potential of the transistor 51 causes the rise in the potential of the node D from V1xe2x88x92Vt to V2 as shown in FIG. 6 by means of the coupling of the channel region in the transistor 51. When this potential V2 is higher than the value (V1+Vt) obtained by adding the threshold voltage Vt of the transistor 51 to the potential V1 of the node A, the transistor 51 is set to a sufficient ON state with the result that the boosted potential supplied to the node A is transmitted to the node B. As a result, as shown in FIG. 6D, the boosted potential V1 is supplied to the word line WL.
In this manner, it is required to sufficiently increase the potential of the node D which is the gate node of the transistor 51 in order to transmit the potential V1 which is boosted from the node A to the node B. However, when the potential of the node D becomes too high so that the potential of the node D exceeds a withstanding voltage of the transistor connected to this node D, for example, the transistor 52, the transistor 52 will be broken.
The potential limiting circuit 53 is provided to restrict the potential of the node D so as to prevent the potential of the node D from exceeding the withstanding voltage of the transistor 52. That is, when the potential of the node D becomes higher than the sum of the threshold voltages of the respective transistors 54 and 55, namely 2 Vt higher than the potential of the node F, the node D is discharged to the node F via a series connection circuit of the transistors 54 and 55 with the result that the potential of the node D is restricted so that the potential does not become a certain potential or more. Here, for example, when the potential of the node F is set to be equal to the potential V1 at the node A, the upper limit of the node D becomes V1+2 Vt.
By the way, in a circuit of FIG. 5, no problem arises when the potential V1 supplied to the node F has a sufficient current supply capability as can be seen in the power supply given from the outside of the chip, and the level is maintained stably. However, in the case where the potential V1 supplied to the node F is generated in the booster circuit or the like in the chip, the current supply capability is low. When the current is consumed with the operation of the other circuit, there is a possibility that the potential V1 at the node F is lowered to a level less than the predetermined value. This leads to the restriction of the potential of the node D to a level less than needed with the result that the potential of the node D does not attain the target value, and a boosted potential having a sufficient value can not be supplied to the word line WL.
In such a situation, conventionally, a circuit shown in FIG. 7 is provided. This circuit is constituted in such a manner that the potential generated in the booster circuit 76 in the chip is supplied to the node F of the potential limiting circuit 53 via a transistor 77 which is diode-connected. Incidentally, the potential generated in the booster circuit 76 is also supplied to the other circuit 78 in the same chip.
In this circuit arrangement, the current is consumed in another circuit 78. Since a gate of the transistor 77 is connected either to the source and the drain to form a diode-connection and the transistor 77 having a rectifying characteristic is connected between the booster circuit 76 and the node F, even when an output potential from the booster circuit 76 is lowered, the potential of the node F is not lowered.
By the way, as shown in FIG. 7, the capacity 71 is connected between the node F and the ground potential. This capacity 71 is provided for stabilizing the potential of the node F. When the potential limiting circuit 53 is operated, an excess charge at the node D is discharged toward the node F. No problem arises when the discharged charge is small as compared with the value of the capacity 71. Otherwise, since the node F is in the floating state, the node F rises to a level higher than the potential set with the output of the booster circuit 76. In this case, the charge of the node D is not discharged, and the intended effect of the potential limiting circuit 53 is lost.
Under these circumstances, it is considered that the value of the capacity 71 is enlarged. However, in the case where a plurality of potential limiting circuits 53 are connected to the node F, and these plurality of potential limiting circuits 53 are operated at the same time, the discharged charge quantity to the node F will become very large. Since it is necessary to make an attempt of increasing the capacity 71 along with the enlargement of the discharged charge quantity, a very large element area for the capacity 71 will be required. This leads to an increase in the chip area.
Then, in order to solve the above problem, furthermore, conventionally, a circuitry shown in FIG. 8 is provided. This circuitry is designed to divide the potential at the node F with a pair of resistors 81 and 82 connected in series between the node F and the ground potential, and compares the divided potential Vdiv with the reference potential Vref with a differential amplifier 83 so that an attempt is made to stabilize the potential at the node F by controlling the conduction of the transistor 84 connected between the node F and the ground potential on the basis of the result of the comparison at the amplifier 83.
That is, an excess increase in the potential of the node F is prevented by comparing the potential Vdiv divided with the pair of resistors 81 and 82 and the reference potential Vref by the differential amplifier 83 and discharging the charge of the node F through the transistor 84 when the potential of the node F becomes too high.
However, in this case, in the case where the boosted potential which is output from the booster circuit 76 is undesirably lowered, there arises a problem in that a charging path disappears for supplying a charge with respect to the node F so that the charge of the node F is undesirably discharged via the resistors 81 and 82, and the potential of the node F is lowered excessively.
The present invention has been made in view of the above circumstances. An object of the invention is to provide a potential change suppressing circuit which is capable of maintaining the boosted potential at a predetermined value at all times without increasing the chip area.
According to a first aspect of the present invention, there is provided a potential change suppressing circuit comprising:
a capacitor connected between a first node and a second node;
a switch for connecting the first node to a first reference potential;
a potential setting circuit which sets the second node to a second reference potential; and
a potential changing circuit which changes a potential of the second node in a direction opposite to a direction of a potential change in the second node in the case where the potential of the first node is changed by a predetermined value or more along with a change in the potential in the second node.
According to another aspect of the present invention, there is provided a potential change suppressing circuit comprising:
a capacitor connected between a first node and a second node;
a switch for connecting the first node to a first reference potential;
a potential setting circuit for setting the second node to a second reference voltage;
a potential change detecting circuit for detecting a potential change in the first node along with the change in the potential in the second node; and
a potential changing circuit having one end connected to the second node for changing a potential of the second node in a direction opposite to a direction of a potential change at the second node on the basis of an output from the potential change detecting circuit in a case where the potential of the first node is changed by a predetermined value or more in the potential change detecting circuit.
According to still another aspect of the present invention, there is provided a potential change suppressing circuit comprising:
means for setting a first node to a first reference potential; and
potential changing means for storing the first reference potential at the first node and changing the potential of the first node in a direction opposite to a shift of the potential in the case where the potential in the first node is shifted from the stored first reference potential.
According to still another aspect of the present invention, there is provided a potential change suppressing circuit comprising:
a first transistor where a word line drive voltage is supplied to one end of a current channel between a source and a drain, and the other end of the current channel between the source and the drain is connected to the word line;
a second transistor where a first potential is supplied to one end of the current channel between the source and the drain, a predetermined bias potential is supplied to the gate, and the other end of the current channel between the source and the drain is connected to the gate of the first transistor;
circuit means which is connected between the gate of the first transistor and the first node and which has a rectifying characteristic which allows current to flow from the gate of the first transistor only in a direction of the first node; and
control means connected to the first node for discharging the first node to lower the potential of the first node in the case where the potential of the first node rises, the control means having,
a capacity connected between the first node and the second node,
switching means for connecting and controlling the second node to the first reference potential, and
potential changing means for changing the potential of the first node in a direction opposite to the direction of the potential change in the first node in the case where the potential of the second node is changed by a predetermined value or more along with a change in the potential in the first node.
According to still another aspect of the present invention, there is provided a potential change suppressing circuit comprising:
a first transistor where a word line drive voltage is supplied to one end of a current channel between a source and a drain, and the other end of the current channel between the source and the drain is connected to the word line;
a second transistor where a first potential is supplied to one end of the current channel between the source and the drain, a predetermined bias potential is supplied to the gate, and the other end of the current channel between the source and the drain is connected to the gate of the first transistor;
circuit means which is connected between the gate of the first transistor and the first node and which has a rectifying characteristic which allows current to flow from the gate of the first transistor only in a direction of the first node; and
control means connected to the first node for discharging the first node to lower the potential of the first node in the case where the potential of the first node rises, the control means having,
a capacity connected between the first node and the second node;
switching means for connecting and controlling the second node to a first reference potential,
potential change detecting means for detecting a change in the potential of the second node along with the change in the first node, and
potential changing means having one end connected to the first node for changing the potential of the first node in a direction opposite to the direction of the potential change in the first node on the basis of an output from the potential change detecting means in the case where the potential of the first node is changed by a predetermined value or more in the potential change detecting means.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.